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r01ds0044ej0100 rev.1.00 page 1 of 47 aug 11, 2011 r8c/3mq group renesas mcu datasheet 1. overview 1.1 features the r8c/3mq group single-chip mcu functions as a low-power-consumption transceiver which supports 2.4 ghz compliant to ieee802.15.4 standard and inco rporates the r8c cpu core , employing sophisticated instructions for a high level of efficien cy. with 1 mbyte of address space, and it is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. integration of many peripheral functions, including multifun ction timer and serial inte rface, reduces the number of system components. the r8c/3mq group has data flash (1 kb 4 blocks) with the background operation (bgo) function. 1.1.1 applications electronic household appliances, office equipment, audio equipment, cons umer equipment, etc. r01ds0044ej0100 rev.1.00 aug 11, 2011
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 2 of 47 aug 11, 2011 1.1.2 specifications tables 1.1 and 1.2 outline the specifications for r8c/3mq group. table 1.1 specifications for r8c/3mq group (1) item function specification cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 62.5 ns (f(bclk) = 16 mhz, vcc = 2.7 to 3.6 v) 125 ns (f(bclk) = 8 mhz, vcc = 2.2 to 3.6 v) 250 ns (f(bclk) = 4 mhz, vcc = 1.8 to 3.6 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash refer to table 1.3 product list for r8c/3mq group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 2 (detection leve l of voltage detection 1 selectable) i/o ports programmable i/o ports cmos i/o ports: 18 (including xcin and xcout), selectable pull-up resistor (for some ports) clock clock generation circuits ? 3 circuits: xin clock oscillation circuit, xcin clock oscillation circuit (32 khz), low-speed on-chip oscillator ? oscillation stop detection: xin cl ock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed cl ock, low-speed clock, low-speed on-chip oscillator), wait mode, stop mode real-time clock (timer re) interrupts ? interrupt vectors: 69 ? external: 11 sources (int 3, key input 8) ? priority levels: 7 levels watchdog timer ? 14 bits 1 (with prescaler) ? reset start selectable ? low-speed on-chip oscillator for watchdog timer selectable dtc (data transfer controller) ? 1 channel ? activation sources: 17 ? transfer modes: 2 (no rmal mode, repeat mode) timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement m ode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer re 8 bits 1 real-time clock mode (count seconds, minu tes, hours, days of week), output compare mode
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 3 of 47 aug 11, 2011 table 1.2 specifications for r8c/3mq group (2) item function specification serial interface (uart0) shared with clock synchronous serial i/o mode and clock asynchronous serial i/o synchronous serial communication unit (ssu) 1 (shared with i 2 c bus) i 2 c bus 1 (shared with ssu) rf rf frequency 2405 mhz to 2480 mhz reception sensitivity -95 dbm transmission output level 0 dbm baseband ? 127-byte transmit ram, 127-byte receive ram 2 ? automatic ack response function ? 26-bit timer: compare function in 3 channels encryption aes aes encryption/decryption (key length 128bits) flash memory ? programming and erasure voltage: vcc = 1.8 to 3.6 v (in cpu rewrite mode) ? programming and erasure endurance: 10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on -board flash rewrite function ? background operation (bgo) function operating frequency/ supply voltage (in single mode) f(bclk) = 16 mhz, vcc = 2.7 to 3.6 v) f(bclk) = 8 mhz (vcc = 2.2 to 3.6v) f(bclk) = 4 mhz, vcc = 1.8 to 3.6 v) note: f(xin) = fixed at 16 mhz
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 4 of 47 aug 11, 2011 note: 1. refer to 5. electrical characteristics for details on the measurement conditions. current consumption (1) rf = tx: 18 ma rf = rx (reception in progress): 25 ma rf = rx (reception standby): 24 ma rf = rx (reception standby)/wait mode: 23 ma rf = idle: 4 ma rf = off: 2.5 ma *the above applies when: f(xin) = 16 mhz, f(bclk)= 4 mh z, and vcc = vccrf = 1.8 to 3.6 v rf = tx: 19 ma rf = rx (reception in progress): 26 ma rf = rx (reception standby): 25 ma rf = rx (reception standby)/wait mode: 23 ma rf = idle: 5 ma rf = off: 3.5 ma *the above applies when: f(xin) = 16 mhz, f(blck) = 8 mhz, and vcc = vccrf = 2.2 to 3.6 v rf = tx: 21.5 ma rf = rx (reception in progress): 28.5 ma rf = rx (reception standby): 27.5 ma rf = rx (reception standby)/wait mode: 23 ma rf = idle: 7.5 ma rf = off: 6 ma *the above applies when: f(xin) = 16 mhz, f(blck) = 16 mhz, and vcc = vccrf = 2.7 to 3.6 v low-speed on-chip oscillator mode (f(bclk) = 15.6 khz): 80 a low-speed clock mode (f(bclk) = 32 khz, flash memory low-power- consumption mode): 95 a low-speed clock mode (f(bclk) = 32 khz, flash memory off/program operation on ram: 45 a wait mode (system clock = xcin (32 kh z)), peripheral func tion clock on: 6 a wait mode (system clock = xcin (32 khz )), peripheral functi on clock off: 4.5 a wait mode (system clock = foco-s (125 khz)), peripheral function clock on: 13 a wait mode (system clock = foco-s (125 khz)), peripheral function clock off: 7.5 a stop mode (all clocks off): 2 a *when vcc = vccrf = 1.8 to 3.6 v and rf = off operating ambient temperature ? 20 c to 85 c (n version) package 40-pin hwqfn package code: pwqn0040kb-a (previous code: 40pjs-a) table 1.2 specifications for r8c/3mq group (2) item function specification
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 5 of 47 aug 11, 2011 1.2 product list table 1.3 lists product list for r8c/3mq group. figure 1.1 shows a part number, me mory size, and package of r8c/3mq group. figure 1.1 part number, memory size, and package of r8c/3mq group table 1.3 product list for r8c/3mq group current of aug 2011 part no. rom capacity ram capacity package type remarks program rom data flash r5f213m6qnnp 32 kbytes 1 kbyte 4 2.5 kbytes pwqn0040kb-a n version r5f213m7qnnp 48 kbytes 1 kbyte 44 kbytes r5f213m8qnnp 64 kbytes 1 kbyte 46 kbytes r5f213maqnnp 96 kbytes 1 kbyte 47 kbytes R5F213MCQNNP 128 kbytes 1 kbyte 4 7.5 kbytes part no. r 5 f 21 3m 8 q n np package type: np: pwqn0040kb-a (0.5-mm pin-pitch, 6-mm square body) classification n: operating ambient temperature -20c to 85c rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/3mq group r8c/3x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 6 of 47 aug 11, 2011 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram r8c cpu core memory rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with the product type. 2. ram size varies with the product type. system clock generation circuit xin-xout xcin-xcout low-speed on-chip osc illator timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer re (8 bits 1) uart or clock synchronous serial i/o (8 bits 1) i 2 c bus or ssu (8 bits 1) peripheral functions watchdog timer (14 bits) rf baseband voltage detection circuit dtc low-speed on-chip oscillator for watchdog timer 6 port p3 1 port p0 8 port p1 3 port p4
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 7 of 47 aug 11, 2011 1.4 pin assignment figure 1.3 shows pin assignment (top view). table 1.4 outlines pin name information by pin number. figure 1.3 pin assignment (top view) notes: 1. the function in parentheses can be assigned to the pin by a program. 2. [ ] indicates the internal function name related to the pin. 3. confirm the pin 1 position on the package by referring to the package dimensions. 4. connect the metal pad (diegnd) of the package?s bottom side to the board?s gnd side. p4_4(/xcout) 30 29 28 27 26 25 35 1 2 3 4 5 6 40 36 37 38 39 7 8 9 16 11 15 14 13 12 24 23 22 32 33 34 19 18 17 vregout2[vco] vccrf[regin] vregout1 vreg1[ifvdd] vreg2[lna/mix/pavdd] vssrf[reggnd] rfiop rfion vssrf1 vssrf2 10 20 21 31 p4_3(/xcin) vcc mode vss1 reset xout xin vss2[oscgnd] vregout3[osc] p1_7/ki7/int1(/traio) p1_6/ki6(/clk0) p1_5/ki5(/int1/rxd0/traio) p1_4/ki4(/txd0/trcclk) p1_3/ki3/trbo (/trcioc) p1_2/ki2(/trciob) p1_1/ki1(/trcioa/trctrg) p1_0/ki0(/trciod) ifrxtp ifrxtn vreg4[plldvdd] p0_4/treo(/trciob)/asw p3_7/sda/sso/trao p3_5/scl/ssck(/trciod) p3_4/ssi(/trcioc) p3_3/int3/scs(/trcclk) p3_1(/trbo) p3_0(/trao) p4_5/int0 vreg3[pllavdd] bottom side: diegnd r8c/3mq group pwqn0040kb-a(40pjs-a) (top view)
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 8 of 47 aug 11, 2011 note: 1. the function in parentheses can be assigned to the pin by a program. table 1.4 pin name information by pin number pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus rf pin other 1 vregout3 2vss2 3xin 4xout 5 reset 6vss1 7mode 8vcc 9(xcin)p4_3 10 (xcout) p4_4 11 p1_7 ki7 /int1 (traio) 12 p1_6 ki6 (clk0) 13 p1_5 ki5 (/int1 ) (traio) (rxd0) 14 p1_4 ki4 (trcclk) (txd0) 15 p1_3 ki3 trbo(/trcioc) 16 p1_2 ki2 (trciob) 17 p1_1 ki1 (trcioa/trctrg) 18 p1_0 ki0 (trciod) 19 ifrxtp 20 ifrxtn 21 vccrf 22 vregout1 23 vreg1 24 vreg2 25 vssrf 26 rfiop 27 rfion 28 vssrf1 29 vssrf2 30 vreg3 31 vregout2 32 vreg4 33 p0_4 treo(/trciob) asw 34 p3_7 trao sso sda 35 p3_5 (trciod) ssck scl 36 p3_4 (trcioc) ssi 37 p3_3 int3 (trcclk) scs 38 p3_1 (trbo) 39 p3_0 (trao) 40 p4_5 int0 bottom side diegnd
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 9 of 47 aug 11, 2011 1.5 pin functions tables 1.5 and 1.6 list pin functions. i: input o: output i/o: input and output table 1.5 pin functions (1) item pin name i/o type description power supply input vcc, vss1 ? apply 1.8 to 3.6 v to the vcc pin. apply 0 v to the vss1 pin. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provided for xin clock oscillation circuit i/o. connect a crystal oscillator between the xin and xout pins. xin clock output xout i/o xcin clock input xcin i these pins are provided for xcin clock oscillation circuit i/o. connect a crystal oscillator between the xcin and xcout pins. xcin clock output xcout o int interrupt input int0 , int1 , int3 i int interrupt input pins. int0 is used as an input pin for timer rb and timer rc. key input interrupt input ki0 to ki7 i key input interrupt input pins. timer ra traio i/o timer ra i/o pin. trao o timer ra output pin. timer rb trbo o timer rb output pin. timer rc trcclk i external clock input pin. trctrg i external trigger input pin. trcioa, trciob, trcioc, trciod i/o timer rc i/o pins. timer re treo o divided clock output pin. serial interface clk0 i/o transfer clock i/o pin. rxd0 i serial data input pin. txd0 o serial data output pin. ssu ssi i/o data i/o pin. scs i/o chip-select signal i/o pin. ssck i/o clock i/o pin. sso i/o data i/o pin. i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin i/o ports p0_4, p1_0 to p1_7, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program.
r8c/3mq group 1. overview r01ds0044ej0100 rev.1.00 page 10 of 47 aug 11, 2011 i: input o: output i/o: input and output table 1.6 pin functions (2) item pin name i/o type description analog power supply input vccrf, vssrf, vssrf1, vssrf2, vss2, diegnd ? apply the same voltage as the vcc of 1.8 v to 3.6 v to vccrf. apply 0 v to vssrf, vssrf1, vssrf2, vss2, and diegnd. vreg1 ? 1.5 v if vdd pin. connect to the vregout1 pin. vreg2 ? 1.5 v lna/mix/pa vdd pin. connect to the vregout1 pin. vreg3 ? 1.5 v pll analog vdd pin. connect to the vregout1 pin. vreg4 ? 1.5 v pll digital vdd pin. connect to the vregout1 pin. regulator output vregout1 ? on-chip regulator output (1.5 v) pin for the analog circuit. connect only a bypass capacitor between pins vregout1 and vss. use only as the power supply for pins vreg1, vreg2, vreg3, and vregf4. vregout2 ? regulator output (1.5 v) pin for the vco circuit. connect only a bypass capacitor between pins vregout2 and vss. do not use as the power supply for other circuits. vregout3 ? regulator output (1.5 v) pin for the xin oscillation circuit. connect only a bypass capacitor between pins vregout3 and vss. do not use as the power supply for other circuits. rf i/o rfiop, rfion i/o rf i/o pins test pins ifrxtn, ifrxtp i/o ports for testing. leave open or apply 0 v. external antenna switch control output asw o signal output pin to control the external antenna switch. if antenna switch control is not required, leave open.
r8c/3mq group 2. central processing unit (cpu) r01ds0044ej0100 rev.1.00 page 11 of 47 aug 11, 2011 2. central processing unit (cpu) figure 2.1 shows the cpu registers. th e cpu contains 13 registers. r0, r1 , r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/3mq group 2. central processing unit (cpu) r01ds0044ej0100 rev.1.00 page 12 of 47 aug 11, 2011 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, arithmetic, an d logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is analogous to a0. a1 can be combined w ith a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starting a ddress of a relocatable interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operati on results in an overflow; otherwise to 0.
r8c/3mq group 2. central processing unit (cpu) r01ds0044ej0100 rev.1.00 page 13 of 47 aug 11, 2011 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when th e i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt reque st is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the conten t is undefined.
r8c/3mq group 3. memory r01ds0044ej0100 rev.1.00 page 14 of 47 aug 11, 2011 3. memory 3.1 r8c/3mq group figure 3.1 is a memory map of r8c/3mq group. the r8c/3mq group has a 1-mbyte address space from addresses 00000h to fffffh. the internal rom (program rom) is al located lower addre sses, beginning with address 0ffffh. however, for products with internal rom (program rom) capacity of 64 kbytes or more, the internal rom is also allocated higher ad dresses, beginning with address 0ffffh. for example, a 32-kbyte internal rom area is allocated addresses 08000h to 0ffffh, and a 96-kbyte internal rom is allocated addresses 04000h to 1bfffh. the fixed interrupt vector table is allocated addresse s 08000h to 0ffffh. the startin g address of each interrupt routine is stored here. the internal rom (data flash) is allocated addresses 03000h to 03fffh. the internal ram is allocated higher addresses, beginn ing with address 00400h. for example, a 2.5-kbyte internal ram area is allocated addresses 00400h to 00dffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfrs) are allocated addresse s 00000h to 002ffh and 02c00h to 02fffh. peripheral function control registers are allocate d here. all unallocated spaces within the sfrs are reserved and cannot be accessed by users. figure 3.1 memory map of r8c/3mq group 0ffffh 0ffdch notes: 1. the data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. the blank areas are reserved and cannot be accessed by users. internal ram size address 0xxxxh 2.5 kbytes 4 kbytes 6 kbytes 7 kbytes 7.5 kbytes 00dffh 013ffh 01bffh 01fffh 021ffh part number internal rom size address 0yyyyh r5f213m6qnnp r5f213m7qnnp r5f213m8qnnp r5f213maqnnp R5F213MCQNNP 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 04000h 04000h 04000h 04000h address zzzzzh ? ? 13fffh 1bfffh 23fffh fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 02fffh 02c00h sfr (refer to 4. special function registers (sfrs) ) zzzzzh 03fffh 03000h internal rom (data flash) (1) internal rom (program rom) undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor address break (reserved) reset 0ffd8h reserved area
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 15 of 47 aug 11, 2011 4. special function registers (sfrs) an sfr (special function regist er) is a control register for a peripheral function. tables 4.1 to 4.11 list the special function registers. table 4.12 lists the id code areas and option function select area. x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. the cwr bit in the rstfr register is set to 0 after power-on and voltage monitor 0 reset. hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. the csproini bit in the ofs register is set to 0. table 4.1 sfr information (1) (0000h to 002fh) (1) address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 00101000b 0007h system clock control register 1 cm1 00101000b 0008h module standby control register mstcr 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source determination register rstfr 0xxxxxxxb (2) 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (3) 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h 002ah 002bh 002ch 002dh 002eh 002fh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 16 of 47 aug 11, 2011 x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. 3. the lvdas bit in the ofs register is set to 1. 4. the lvdas bit in the ofs register is set to 0. 5. can be selected by the bank0intsel bit in the bbtxrxmode4 register. table 4.2 sfr information (2) (0030h to 006fh) (1) address register symbol after reset 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h 0034h voltage detection register 2 vca2 00h (3) 00100000b (4) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circuit control register vw0c 1100x010b (3) 1100x011b (4) 0039h voltage monitor 1 circuit control register vw1c 10001010b 003ah wdt detection flag vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h bb timer compare 2 interrupt control register bbtim2ic xxxxx000b 0043h 0044h 0045h 0046h 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h 004ah timer re interrupt control register treic xxxxx000b 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh 004fh ssu interrupt control register/iic bus interrupt control register (2) ssuic/iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h 0054h bank 0 reception complete/idle interrupt control register (5) bbrx0ic/bbidelic xxxxx000b 0055h 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch bb timer compare 1 interrupt control register bbtim1ic xx00x000b 005dh int0 interrupt control register int0ic xx00x000b 005eh cca complete interrupt control register bbccaic xxxxx000b 005fh bb timer compare 0 interrupt control register bbtim0ic xxxxx000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch address filter interrupt control register bbadfic xxxxx000b 006dh transmit overrun interrupt control register bbtxoric xxxxx000b 006eh transmission complete interrupt control register bbtxic xx00xx00b 006fh receive overrun 1 interrupt control register bbrxor1ic xxxxx000b
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 17 of 47 aug 11, 2011 x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. can be selected by the bank1intsel bit in the bbtxrxmode4 register. 3. can be selected by the ror0intsel bit in the bbtxrxmode4 register. table 4.3 sfr information (3) (0070h to 00afh) (1) address register symbol after reset 0070h pll lock detection interrupt control register bbpllic xxxxx000b 0071h receive overrun 0/calibration comp lete interrupt control register (3) bbrxor0ic/bbcalic xxxxx000b 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h bank 1 reception complete/clock regulator interrupt control register (2) bbrx1ic/bbcregic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh 0080h dtc activation control register dtctl 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dtc activation enable register 0 dtcen0 00h 0089h dtc activation enable register 1 dtcen1 00h 008ah dtc activation enable register 2 dtcen2 00h 008bh dtc activation enable register 3 dtcen3 00h 008ch 008dh dtc activation enable register 5 dtcen5 00h 008eh dtc activation enable register 6 dtcen6 00h 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh xxh 00a3h 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh xxh 00a7h 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 18 of 47 aug 11, 2011 x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.4 sfr information (4) (00b0h to 011fh) (1) address register symbol after reset 00b0h : 00dfh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 xxh 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h 0107h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 19 of 47 aug 11, 2011 x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. table 4.5 sfr information (5) (0120h to 019fh) (1) address register symbol after reset 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 00h 0127h 0128h timer rc general register a trcgra ffh ffh 0129h 012ah timer rc general register b trcgrb ffh ffh 012bh 012ch timer rc general register c trcgrc ffh ffh 012dh 012eh timer rc general register d trcgrd ffh ffh 012fh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 01111111b 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh : 0180h timer ra pin select register trasr 00h 0181h timer rb/rc pin select register trbrcsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h 0185h 0186h 0187h 0188h uart0 pin select register u0sr 00h 0189h 018ah 018bh 018ch ssu/iic pin select register ssuiicsr 00h 018dh 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h ss bit counter register ssbr 11111000b 0194h ss transmit data register l / ii c bus transmit data register (2) sstdr / icdrt ffh 0195h ss transmit data register h (2) sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr / icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl / iccr2 01111101b 019ah ss mode register / iic bus mode register (2) ssmr / icmr 00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 019ch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 019eh 019fh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 20 of 47 aug 11, 2011 x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. table 4.6 sfr information (6) (01a0h to 02ffh) (1) address register symbol after reset 01a0h : 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 00h 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh 01c0h address match interrupt register 0 rmad0 xxh xxh 0000xxxxb 01c1h 01c2h 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh xxh 0000xxxxb 01c5h 01c6h 01c7h address match interrupt enable register 1 aier1 00h 01c8h : 01dfh 01e0h pull-up control register 0 pur0 00h 01e1h pull-up control register 1 pur1 00h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h port p1 drive capacity control register p1drr 00h 01f1h 01f2h drive capacity control register 0 drr0 00h 01f3h drive capacity control register 1 drr1 00h 01f4h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h 01f8h 01f9h 01fah external input enable register 0 inten 00h 01fbh 01fch int input filter select register 0 intf 00h 01fdh 01feh key input enable register 0 kien 00h 01ffh key input enable register 1 ki1en 00h 0200h : 02ffh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 21 of 47 aug 11, 2011 x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.7 sfr information (7) (2c00h to 2c6fh) (1) address register symbol after reset 2c00h dtc transfer vector area xxh 2c01h dtc transfer vector area xxh 2c02h dtc transfer vector area xxh 2c03h dtc transfer vector area xxh 2c04h dtc transfer vector area xxh 2c05h dtc transfer vector area xxh 2c06h dtc transfer vector area xxh 2c07h dtc transfer vector area xxh 2c08h dtc transfer vector area xxh 2c09h dtc transfer vector area xxh 2c0ah dtc transfer vector area xxh : dtc transfer vector area xxh : dtc transfer vector area xxh 2c3ah dtc transfer vector area xxh 2c3bh dtc transfer vector area xxh 2c3ch dtc transfer vector area xxh 2c3dh dtc transfer vector area xxh 2c3eh dtc transfer vector area xxh 2c3fh dtc transfer vector area xxh 2c40h dtc control data 0 dtcd0 xxh 2c41h xxh 2c42h xxh 2c43h xxh 2c44h xxh 2c45h xxh 2c46h xxh 2c47h xxh 2c48h dtc control data 1 dtcd1 xxh 2c49h xxh 2c4ah xxh 2c4bh xxh 2c4ch xxh 2c4dh xxh 2c4eh xxh 2c4fh xxh 2c50h dtc control data 2 dtcd2 xxh 2c51h xxh 2c52h xxh 2c53h xxh 2c54h xxh 2c55h xxh 2c56h xxh 2c57h xxh 2c58h dtc control data 3 dtcd3 xxh 2c59h xxh 2c5ah xxh 2c5bh xxh 2c5ch xxh 2c5dh xxh 2c5eh xxh 2c5fh xxh 2c60h dtc control data 4 dtcd4 xxh 2c61h xxh 2c62h xxh 2c63h xxh 2c64h xxh 2c65h xxh 2c66h xxh 2c67h xxh 2c68h dtc control data 5 dtcd5 xxh 2c69h xxh 2c6ah xxh 2c6bh xxh 2c6ch xxh 2c6dh xxh 2c6eh xxh 2c6fh xxh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 22 of 47 aug 11, 2011 x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.8 sfr information (8) (2c70h to 2cafh) (1) address register symbol after reset 2c70h dtc control data 6 dtcd6 xxh 2c71h xxh 2c72h xxh 2c73h xxh 2c74h xxh 2c75h xxh 2c76h xxh 2c77h xxh 2c78h dtc control data 7 dtcd7 xxh 2c79h xxh 2c7ah xxh 2c7bh xxh 2c7ch xxh 2c7dh xxh 2c7eh xxh 2c7fh xxh 2c80h dtc control data 8 dtcd8 xxh 2c81h xxh 2c82h xxh 2c83h xxh 2c84h xxh 2c85h xxh 2c86h xxh 2c87h xxh 2c88h dtc control data 9 dtcd9 xxh 2c89h xxh 2c8ah xxh 2c8bh xxh 2c8ch xxh 2c8dh xxh 2c8eh xxh 2c8fh xxh 2c90h dtc control data 10 dtcd10 xxh 2c91h xxh 2c92h xxh 2c93h xxh 2c94h xxh 2c95h xxh 2c96h xxh 2c97h xxh 2c98h dtc control data 11 dtcd11 xxh 2c99h xxh 2c9ah xxh 2c9bh xxh 2c9ch xxh 2c9dh xxh 2c9eh xxh 2c9fh xxh 2ca0h dtc control data 12 dtcd12 xxh 2ca1h xxh 2ca2h xxh 2ca3h xxh 2ca4h xxh 2ca5h xxh 2ca6h xxh 2ca7h xxh 2ca8h dtc control data 13 dtcd13 xxh 2ca9h xxh 2caah xxh 2cabh xxh 2cach xxh 2cadh xxh 2caeh xxh 2cafh xxh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 23 of 47 aug 11, 2011 x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.9 sfr information (9) (2cb0h to 2cefh) (1) address register symbol after reset 2cb0h dtc control data 14 dtcd14 xxh 2cb1h xxh 2cb2h xxh 2cb3h xxh 2cb4h xxh 2cb5h xxh 2cb6h xxh 2cb7h xxh 2cb8h dtc control data 15 dtcd15 xxh 2cb9h xxh 2cbah xxh 2cbbh xxh 2cbch xxh 2cbdh xxh 2cbeh xxh 2cbfh xxh 2cc0h dtc control data 16 dtcd16 xxh 2cc1h xxh 2cc2h xxh 2cc3h xxh 2cc4h xxh 2cc5h xxh 2cc6h xxh 2cc7h xxh 2cc8h dtc control data 17 dtcd17 xxh 2cc9h xxh 2ccah xxh 2ccbh xxh 2ccch xxh 2ccdh xxh 2cceh xxh 2ccfh xxh 2cd0h dtc control data 18 dtcd18 xxh 2cd1h xxh 2cd2h xxh 2cd3h xxh 2cd4h xxh 2cd5h xxh 2cd6h xxh 2cd7h xxh 2cd8h dtc control data 19 dtcd19 xxh 2cd9h xxh 2cdah xxh 2cdbh xxh 2cdch xxh 2cddh xxh 2cdeh xxh 2cdfh xxh 2ce0h dtc control data 20 dtcd20 xxh 2ce1h xxh 2ce2h xxh 2ce3h xxh 2ce4h xxh 2ce5h xxh 2ce6h xxh 2ce7h xxh 2ce8h dtc control data 21 dtcd21 xxh 2ce9h xxh 2ceah xxh 2cebh xxh 2cech xxh 2cedh xxh 2ceeh xxh 2cefh xxh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 24 of 47 aug 11, 2011 x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.10 sfr information (10) (2cf0h to 2d2fh) (1) address register symbol after reset 2cf0h dtc control data 22 dtcd22 xxh 2cf1h xxh 2cf2h xxh 2cf3h xxh 2cf4h xxh 2cf5h xxh 2cf6h xxh 2cf7h xxh 2cf8h dtc control data 23 dtcd23 xxh 2cf9h xxh 2cfah xxh 2cfbh xxh 2cfch xxh 2cfdh xxh 2cfeh xxh 2cffh xxh 2d00h baseband control register bbcon 00h 2d01h transmit/receive reset register bbtxrxrst 00h 2d02h transmit/receive mode register 0 bbtxrxmode0 00h 2d03h transmit/receive mode register 1 bbtxrxmode1 00h 2d04h receive frame length register bbrxflen 00h 2d05h receive data counter register bbrxcount 00h 2d06h rssi/cca result r egister bbrssiccarslt 00h 2d07h transmit/receive status register 0 bbtxrxst0 80h 2d08h transmit frame length register bbtxflen 00h 2d09h transmit/receive mode register 2 bbtxrxmode2 30h 2d0ah transmit/receive mode register 3 bbtxrxmode3 00h 2d0bh receive level threshold set register bblvlvth 80h 2d0ch transmit/receive control register bbtxrxcon 00h 2d0dh csma control register 0 bbcsmacon0 00h 2d0eh cca level threshold set register bbccavth 80h 2d0fh transmit/receive status register 1 bbtxrxst1 00h 2d10h rf control register bbrfcon 00h 2d11h transmit/receive mode register 4 bbtxrxmode4 00h 2d12h csma control register 1 bbcsmacon1 9ch 2d13h csma control register 2 bbcsmacon2 05h 2d14h pan identifier register bbpanid 00h 00h 2d15h 2d16h short address register bbshortad 00h 00h 2d17h 2d18h extended address register bbextendad0 00h 2d19h 00h 2d1ah bbextendad1 00h 2d1bh 00h 2d1ch bbextendad2 00h 2d1dh 00h 2d1eh bbextendad3 00h 2d1fh 00h 2d20h timer read-out register 0 bbtimeread0 00h 2d21h 00h 2d22h timer read-out register 1 bbtimeread1 00h 2d23h 00h 2d24h timer compare 0 register 0 bbcomp0reg0 00h 2d25h 00h 2d26h timer compare 0 register 1 bbcomp0reg1 00h 2d27h 00h 2d28h timer compare 1 register 0 bbcomp1reg0 00h 2d29h 00h 2d2ah timer compare 1 register 1 bbcomp1reg1 00h 2d2bh 00h 2d2ch timer compare 2 register 0 bbcomp2reg0 00h 2d2dh 00h 2d2eh timer compare 2 register 1 bbcomp2reg1 00h 2d2fh 00h
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 25 of 47 aug 11, 2011 x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.11 sfr information (11) (2d30h to 2fffh) (1) address register symbol after reset 2d30h time stamp register 0 bbtstamp0 00h 00h 2d31h 2d32h time stamp register 1 bbtstamp1 00h 00h 2d33h 2d34h timer control register bbtimecon 00h 2d35h backoff period register bbboffprod 00h 2d36h 2d37h 2d38h 2d39h 2d3ah pll division register 0 bbplldivl 65h 2d3bh pll division register 1 bbplldivh 09h 2d3ch transmit output power register bbtxoutpwr 00h 2d3dh rssi offset register bbrssiofs f6h 2d3eh 2d3fh 2d40h : 2d45h 2d46h automatic ack response timing adjustment register bbackrtntimg 22h 2d47h : 2d63h 2d64h 2d65h 2d66h 2d67h 2d68h verification mode set register bbevareg 00h 2d69h 2d6ah 2d6bh 2d6ch 2d6dh 2d6eh 2d6fh 2d70h 2d71h 2d72h 2d73h 2d74h 2d75h 2d76h idle wait set register bbidelwait 01h 2d77h 2d78h 2d79h 2d7ah antsw output timing set register bbantswtimg 72h 2d7bh 2d7ch rf initial set register bbrfini xxh xxh 2d7dh 2d7eh 2d7fh 2d80h 2d81h 2d82h antsw control register bbantswcon 00h 2d83h : 2dffh 2e00h transmit ram transmit_ram_start : transmit ram 2e7eh transmit ram transmit_ram_end 2e7fh 2d80h receive ram recieve_ram_start : receive ram 2efeh receive ram recieve_ram_end 2effh 2f00h : 2fffh
r8c/3mq group 4. special function registers (sfrs) r01ds0044ej0100 rev.1.00 page 26 of 47 aug 11, 2011 table 4.12 id code areas and option function select area notes: 1. the option function select area is allocated in the flash memo ry, not in the sfrs. set appropria te values as rom data by a pr ogram. do not write additions to the option function select area. if the block including the option function select area is erased, th e option function select area is set to ffh. at shipment, the option function select area is set to ffh. it is set to the written value after written by the user. 2. the id code areas are allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not write additions to the id code areas. if the block includ ing the id code areas is erased, the id code areas are set to f fh. at shipment, the id code areas are set to ffh. they are set to the written value after written by the user. address area name symbol after reset : ffdbh option function select register 2 ofs2 (note 1) : ffdfh id1 (note 2) : ffe3h id2 (note 2) : ffebh id3 (note 2) : ffefh id4 (note 2) : fff3h id5 (note 2) : fff7h id6 (note 2) : fffbh id7 (note 2) : ffffh option function select register ofs (note 1)
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 27 of 47 aug 11, 2011 5. electrical characteristics table 5.1 absolute maximum ratings symbol parameter condition rated value unit vcc digital supply voltage ? 0.3 to 3.8 v vccrf analog supply voltage ? 0.3 to 3.8 v v i input voltage reset , mode, p0_4, p1, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5 ? 0.3 to v cc + 0.3 v v o output voltage p0_4, p1, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5 ? 0.3 to v cc + 0.3 v vrfio rf i/o pins rfiop, rfion ? 0.3 to 2.1 v vtestio test ports ifrxtp, ifrxtn ? 0.3 to 2.1 v vanain 1.5 v analog supply (input) vreg1, vreg2, vreg3, vreg4 ? 0.3 to 2.1 v vanaout 1.5 v analog supply (output) vregout1, vregout2, vregout3 ? 0.3 to 2.1 v vxinout main clock i/o xin, xout ? 0.3 to 2.1 v p d power dissipation ? 20 c t opr 85 c300mw t opr operating ambient temperature (1) during mcu operation under the conditions other than (2) and (3) below. ? 20 to 85 c (2) during programming and erasing of the flash memory using a serial programmer or parallel programmer. 0 to 60 (3) during on-chip debugging with the e8a emulator connected 10 to 35 t stg storage temperature ? 65 to 150 c
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 28 of 47 aug 11, 2011 notes: 1. v cc = 1.8 to 3.6 v and t opr = ? 20c to 85c, unless otherwise specified. 2. the average output current indicates the average value of current measured during 100 ms. table 5.2 recommended operating conditions (1) symbol parameter conditions standard unit min. typ. max. vcc digital supply voltage (1) during mcu operation under the conditions other than (2) and (3) below. 1.8 3.3 3.6 v (2) during programming and erasing of the flash memory using a serial programmer or parallel programmer. 2.7 ? 3.6 (3) during on-chip debugging with the e8a emulator connected 2.7 ? 3.6 vccrf analog supply voltage 1.8 3.3 3.6 v vss/ vss2/ vssrf/ vssrf1/ vssrf2/ diegnd supply voltage vss1, vss2, vssrf, vssrf1, vssrf2, diegnd ?0?v v ih input ?h? voltage other than cmos input 0.8 v cc ?v cc v cmos input input level switching function (i/o port) input level selection: 0.35 v cc 2.7 v v cc 3.6 v 0.55 v cc ?v cc v 1.8 v v cc < 2.7 v 0.65 v cc ?v cc v input level selection: 0.5 v cc 2.7 v v cc 3.6 v 0.7 v cc ?v cc v 1.8 v v cc < 2.7 v 0.8 v cc ?v cc v input level selection: 0.7 v cc 2.7 v v cc 3.6 v 0.85 v cc ?v cc v 1.8 v v cc < 2.7 v 0.85 v cc ?v cc v v il input ?l? voltage other than cmos input 0 ? 0.2 v cc v cmos input input level switching function (i/o port) input level selection: 0.35 v cc 2.7 v v cc 3.6 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection: 0.5 v cc 2.7 v v cc 3.6 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection: 0.7 v cc 2.7 v v cc 3.6 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? ? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? ? 80 ma i oh(peak) peak output ?h? current drive capacity low ? ? ? 10 ma drive capacity high ? ? ? 40 ma i oh(avg) average output ?h? current drive capacity low ? ? ? 5ma drive capacity high ? ? ? 20 ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ? ? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ??80ma i ol(peak) peak output ?l? current drive capacity low ? ? 10 ma drive capacity high ? ? 40 ma i ol(avg) average output ?l? current drive capacity low ? ? 5 ma drive capacity high ? ? 20 ma f (xin) xin clock input oscillation frequency 1.8 v v cc 3.6 v ? 16 ? mhz f (xcin) xcin clock input oscillation frequency 1.8 v v cc 3.6 v 30 32.768 35 khz ? system clock frequency f(xin)=16 mhz 1.8 v v cc 3.6 v ? ? 16 mhz f (bclk) cpu clock frequency f(xin)=16 mhz 2.7 v v cc 3.6 v ? ? 16 mhz 2.2 v v cc < 2.7 v ? ? 8 1.8 v v cc < 2.2 v ? ? 4
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 29 of 47 aug 11, 2011 figure 5.1 ports p0, p1, p3 and p4 timing measurement circuit p0 p1 p3 p4 30 pf
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 30 of 47 aug 11, 2011 notes: 1. v cc = 2.7 to 3.6 v and t opr = 0 to 60c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 1,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed.) 4. in a system that executes multiple programming operations, t he actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on t he erasure endurance of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.3 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 1,000 (3) ??times ? byte program time ? 80 500 s ? block erase time ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? s ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s td (cmdrst- ready) time from when command is forcibly stopped until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage cpu rewrite mode 1.8 ? 3.6 v standard serial i/o mode 2.7 ? 3.6 parallel i/o mode 2.7 ? 3.6 ? read voltage 1.8 ? 3.6 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55c 20 ? ? year
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 31 of 47 aug 11, 2011 notes: 1. v cc = 1.8 to 3.6 v and t opr = ? 20c to 85c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each bl ock can be erased n times. fo r example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed.) 4. in a system that executes multiple programming operations, t he actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, averaging the erasure e ndurance between blocks a to d can further reduce the actual erasure endurance. it is also advisable to retain data on the erasure endurance of eac h block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the pow er supply is off or t he clock is not supplied. table 5.4 flash memory (data flash block a to block d) electric al characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ??times ? byte program time (program/erase endurance 1,000 times) ? 160 1500 s ? byte program time (program/erase endurance > 1,000 times) ? 300 1500 s ? block erase time (program/erase endurance 1,000 times) ?0.2 1 s ? block erase time (program/erase endurance > 1,000 times) ?0.3 1 s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? s ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s td (cmdrst- ready) time from when command is forcibly stopped until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage cpu rewrite mode 1.8 ? 3.6 v standard serial i/o mode 2.7 ? 3.6 parallel i/o mode 2.7 ? 3.6 ? read voltage 1.8 ? 3.6 v ? program, erase temperature cpu rewrite mode ? 20 ? 85 c standard serial i/o mode 0 ? 60 parallel i/o mode 0 ? 60 ? data hold time (7) ambient temperature = 55c 20 ? ? year
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 32 of 47 aug 11, 2011 figure 5.2 time delay until suspend notes: 1. the measurement condition is v cc = 1.8 v to 3.6 v and t opr = ? 20c to 85c. 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. 3. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . notes: 1. the measurement condition is v cc = 1.8 v to 3.6 v and t opr = ? 20c to 85c. 2. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 3. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 4. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. table 5.5 voltage detection 0 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 1.80 1.90 2.05 v ? voltage detection 0 circuit response time (3) at the falling of v cc from 3.6 v to (vdet0_0 ? 0.1) v ? 6 150 s ? voltage detection circuit self power consumption vca25 = 1, v cc = 3.0 v ? 1.5 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ? ? 100 s table 5.6 voltage detection 1 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_2 (2) at the falling of v cc 2.30 2.50 2.70 v voltage detection level vdet1_5 (2) at the falling of v cc 2.75 2.95 3.15 v ? hysteresis width at the rising of v cc in voltage detection 1 circuit ?0.07? v ? voltage detection 1 circuit response time (3) at the falling of v cc from 3.6 v to (vdet1_0 ? 0.1) v ? 60 150 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 3.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ? ? 100 s fst6 bit suspend request (fmr21 bit) fixed time t d(sr-sus) clock-dependent time access restart fst6, fst7: bit in fst register fmr21: bit in fmr2 register fst7 bit
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 33 of 47 aug 11, 2011 notes: 1. the measurement condition is t opr = ? 20c to 85c, unless otherwise specified. 2. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 5.3 power-on reset circuit electrical characteristics table 5.7 power-on reset circuit (2) symbol parameter condition standard unit min. typ. max. t rth external power v cc rise gradient (1) 0 ? 50,000 mv/msec notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit of user?s manual: hardware for details. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 reset disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) external power v cc t rth t rth 1 f oco-s 32 1 f oco-s 32
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 34 of 47 aug 11, 2011 note: 1. v cc = 1.8 v to 3.6 v and t opr = ? 20c to 85c, unless otherwise specified. note: 1. v cc = 1.8 v to 3.6 v and t opr = ? 20c to 85c, unless otherwise specified. notes: 1. the measurement condition is v cc = 1.8 to 3.6 v and t opr = 25c. 2. waiting time until the internal power supp ly generation circuit stab ilizes during power-on. notes: 1. v cc = 1.8 v to 3.6 v and t opr = ? 20c to 85c, unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.8 system clock low-speed on-chip os cillator circuit elect rical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 100 125 150 khz ? oscillation stability time ? 30 100 s table 5.9 watchdog timer low-speed on-chip osc illator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-wdt low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation stability time ? 30 100 s table 5.10 power supply circui t timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabili zation during power-on (2) ? ? 2,000 s table 5.11 timing requirements of sync hronous serial communication unit (ssu) (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ? ? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ? ? 1 t cyc (2) slave ? ? 1 s t fall ssck clock falling time master ? ? 1 t cyc (2) slave ? ? 1 s t su sso, ssi data input setup time 100 ? ? ns t h sso, ssi data input hold time 1 ? ? t cyc (2) t lead scs setup time slave 1t cyc + 50 ? ? ns t lag scs hold time slave 1t cyc + 50 ? ? ns t od sso, ssi data output delay time ? ? 1.5 t cyc (2) t sa ssi slave access time 2.7 v v cc 3.6 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 3.6 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 35 of 47 aug 11, 2011 figure 5.4 i/o timing of synchronous serial communication unit (ssu) (master) v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 36 of 47 aug 11, 2011 figure 5.5 i/o timing of synchronous seri al communication unit (ssu) (slave) v ih or v oh v il or v ol scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 37 of 47 aug 11, 2011 figure 5.6 i/o timing of synchronous serial communication unit (ssu) (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v il or v ol
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 38 of 47 aug 11, 2011 notes: 1. v cc = 1.8 v to 3.6 v and t opr = ? 20c to 85c, unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.12 timing requirements of i 2 c bus interface symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ??ns t sclh scl input ?h? width 3t cyc + 300 (2) ??ns t scll scl input ?l? width 5t cyc + 500 (2) ??ns t sf scl, sda input fall time ? ? 300 ns t sp scl, sda input spike pulse rejection time ? ? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ??ns t stah start condition input hold time 3t cyc (2) ??ns t stas retransmit start condi tion input setup time 3t cyc (2) ??ns t stop stop condition input setup time 3t cyc (2) ??ns t sdas data input setup time 1t cyc + 40 (2) ??ns t sdah data input hold time 10 ? ? ns sda scl notes: 1. start condition 2. stop condition 3. retransmit start condition t buf v ih v il p (2) s (1) t stah t sclh t scll t sf t sr t scl t sdah sr (3) p (2) t sdas t stas t sp t stop
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 39 of 47 aug 11, 2011 table 5.13 electrical characteristics (1) [1.8 v v cc 3.6 v] (t opr = ? 20c to 85c, unless otherwise specified) symbol parameter condition standard unit min. typ. max. icc power supply current single-chip mode, output pins are open, other pins are vss high-speed clock mode xin clock oscillator on f(xin) = 16 mhz xcin clock oscillator on f(xcin) = 32 khz low-speed on-chip oscillator on foco-s = 125 khz system clock = xin cpu clock = divide-by-4, (f(bclk) = 4 mhz) 1.8 v vcc 3.6 v rf = off ? 2.5 ? ma rf = idle ? 4.0 ? ma rf = tx ? 18 ? ma rf = rx (reception standby) ? 24 ? ma rf = rx (reception in progress) ?25? ma cpu clock = divide-by-2, (f(bclk) = 8 mhz) 2.2 v vcc 3.6 v rf = off ? 3.5 ? ma rf = idle ? 5.0 ? ma rf = tx ? 19 ? ma rf = rx (reception standby) ?25? ma rf = rx (reception in progress) ?26? ma cpu clock = no division (f(bclk) = 16 mhz) 2.7 v vcc 3.6 v rf = off ? 6.0 ? ma rf = idle ? 7.5 ? ma rf = tx ? 21.5 ? ma rf = rx (reception standby) ? 27.5 ? ma rf = rx (reception in progress) ? 28.5 ? ma low-speed on-chip oscillator mode xin clock off, xcin clock off, low-speed on-chip oscillator on: foco-s = 125 khz system clock = foco-s, cpu clock = divide-by-8 fmr27 = 1, vca20 = 0 (flash memory low-current-consumption read mode) rf = off ? 80 ? a low-speed clock mode xin clock off xcin clock oscillator on f(xcin) = 32 khz low-speed on-chip oscillator off system clock = xcin cpu clock = no division fmr27 = 1 vca20 = 0 (flash memory low-current- consumption read mode) rf = off ? 95 ? a fmstp = 1 vca20 = 0 (flash memory off, program operation on ram) rf = off ? 45 ? a wait mode xin clock oscillator on: f(xin) = 16 mhz xcin clock oscillator on: f(xcin) = 32 khz low-speed on-chip oscillator on: foco-s = 125 khz system clock = xin while a wait instruction is executed rf = rx (reception standby) ?23? ma wait mode xin clock off xcin clock oscillator on f(xcin) = 32 khz low-speed on-chip oscillator off system clock = xcin while a wait instruction is executed peripheral function clock on vca26 = vca25 = 0 vca20 = 1 (voltage detection circuit stopped, internal power consumption enabled) rf = off ? 6.0 ? a peripheral function clock off vca26 = vca25 = 0 vca20 = 1 (voltage detection circuit stopped, internal power consumption enabled) rf = off ? 4.5 ? a wait mode xin clock off xcin clock oscillator on low-speed on-chip oscillator on foco-s = 125 khz system clock = foco-s while a wait instruction is executed peripheral function clock on vca26 = vca25 = 0 vca20 = 1 (voltage detection circuit stopped, internal low power consumption enabled) rf = off ? 13.0 ? a peripheral function clock off vca26 = vca25 = 0 vca20 = 1 (voltage detection circuit stopped, internal low power consumption enabled) rf = off ? 7.5 ? a stop mode (topr = 25c) xin clock off, xcin clock off, low-speed on-chip oscillator off, vca26 = vca25 = 0 (voltage detection circuit stopped) rf = off ? 2.0 ? a
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 40 of 47 aug 11, 2011 note: 1. 2.7 v v cc 3.6 v, t opr = ? 20c to 85c, and f(xin) =16 mhz, unless otherwise specified. table 5.14 electrical characteristics (2) [2.7 v v cc 3.6 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage p0_4, p1, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5 drive capacity high i oh = ? 5 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage p0_4, p1, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5 drive capacity high i ol = 5 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , ki4 , ki6 , ki7 , traio, trcioa, trciob, trcioc, trciod, trctrg, trcclk, rxd0, clk0, ssi, scl, sda, sso vcc = 3.0 v 0.1 0.4 ? v reset vcc = 3.0 v 0.1 0.5 ? v i ih input ?h? current v i = 3 v, v cc = 3.0 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 3.0 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 3.0 v 42 84 168 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? 3.6 v
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 41 of 47 aug 11, 2011 timing requirements (v cc = 3 v, t opr = ? 20c to 85c, unless otherwise specified) figure 5.8 traio input timing diagram when v cc = 3 v figure 5.9 serial interface timing diagram when v cc = 3 v table 5.15 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns table 5.16 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time when an external clock is selected 300 ? ns t w(ckh) clk0 input ?h? width 150 ? ns t w(ckl) clk0 input ?l? width 150 ? ns t d(c-q) txd0 output delay time ? 120 ns t h(c-q) txd0 hold time 0?ns t su(d-c) rxd0 input setup time 30 ? ns t h(c-d) rxd0 input hold time 90 ? ns t h(c-q) txd0 output delay time when an internal clock is selected ? 30 ns t su(d-c) rxd0 input setup time 120 ? ns t h(c-d) rxd0 input hold time 90 ? ns traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio) t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clk0 txd0 rxd0 v cc = 3 v
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 42 of 47 aug 11, 2011 notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.10 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 3 v table 5.17 external interrupt inti (i = 0, 1, 3) input, key input interrupt kii (i = 0 to 7) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 380 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 380 (2) ?ns t w(inl) t w(inh) v cc = 3 v inti input (i = 0, 1, 3) kii input (i = 0 to 7)
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 43 of 47 aug 11, 2011 note: 1. 1.8 v v cc < 2.7 v, t opr = ? 20c to 85c, and f(xin) = 16 mhz, unless otherwise specified. table 5.18 electrical characteristics (3) [1.8 v v cc < 2.7 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage p0_4, p1, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5 drive capacity high i oh = ? 2 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage p0_4, p1, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5 drive capacity high i ol = 2 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , ki4 , ki6 , ki7 , traio, trcioa, trciob, trcioc, trciod, trctrg, trcclk, rxd0, clk0, ssi, scl, sda, sso vcc = 2.2 v 0.05 0.20 ? v reset vcc = 2.2 v 0.05 0.20 ? v i ih input ?h? current v i = 2.2 v, v cc = 2.2 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 2.2 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 2.2 v 70 140 300 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? 3.6 v
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 44 of 47 aug 11, 2011 timing requirements (v cc = 2.2 v, t opr = ? 20c to 85c, unless otherwise specified) figure 5.11 traio input ti ming diagram when v cc = 2.2 v figure 5.12 serial interface timing diagram when v cc = 2.2 v table 5.19 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns table 5.20 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time when an external clock is selected 800 ? ns t w(ckh) clk0 input ?h? width 400 ? ns t w(ckl) clk0 input ?l? width 400 ? ns t d(c-q) txd0 output delay time ? 200 ns t h(c-q) txd0 hold time 0?ns t su(d-c) rxd0 input setup time 150 ? ns t h(c-d) rxd0 input hold time 90 ? ns t h(c-q) txd0 output delay time when an internal clock is selected ? 200 ns t su(d-c) rxd0 input setup time 150 ? ns t h(c-d) rxd0 input hold time 90 ? ns traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clk0 txd0 rxd0 v cc = 2.2 v
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 45 of 47 aug 11, 2011 notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.13 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 2.2 v table 5.21 external interrupt inti (i = 0, 1, 3) input, key input interrupt kii (i = 0 to 7) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 1000 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 1000 (2) ?ns t w(inl) t w(inh) v cc = 2.2 v inti input (i = 0, 1, 3) kii input (i = 0 to 7)
r8c/3mq group 5. electrical characteristics r01ds0044ej0100 rev.1.00 page 46 of 47 aug 11, 2011 note: 1. notes on ffc certification testing when using 26 ch (2480 mhz), adjust the transmit power to meet the fcc requirements and standards at 2483.5 mhz. table 5.22 transceiver tran smission characteristics (vcc = vccrf = 3.3 v, topr = 25c, unless otherwise specified) parameter condition standard ieee802.15.4 standard unit min. typ. max. internal voltage ? 1.45 ? ? v nominal output power ?3 0 3 ?3 or more dbm transmit bit rate ? 250 ? 250 kbps transmit chip rate ? 2000 ? 2000 kchips/s programmable output power range 32 steps ? 32 ? 32 steps db harmonics 2nd harmonics external not ch filter ? ? ?47.2 ?41.2 or less dbm 3rd harmonics ? ? ?47.2 ? spurious emission 30 ? 88 mhz maximum output power, renesas evaluation board ? ? ?55.2 fcc dbm 88 ? 216 mhz ? ? ?51.7 fcc 216 ? 960 mhz ? ? ?49.2 fcc 960 ? 1000 mhz ? ? ?41.2 fcc 1 ? 12.75 ghz ? ? ?41.2 fcc (1) 1.8 ? 1.9 ghz ? ? ?47 etsi 5.15 ? 5.3 ghz ? ? ?47 etsi error vector magnitude evm 1000 chips ? ? 35 35 or less % power spectral density absolute limit |f-fc| > 3.5 mhz ? ? ?30 ?30 or less dbm relative limit |f-fc| > 3.5 mhz ? ? ?20 ?20 or less db frequency tolerance including crystal 20 ppm ?40 ? 40 within 40 ppm table 5.23 transceiver reception characteristics (vcc = vccrf = 3.3 v, topr = 25c, unless otherwise specified) parameter condition standard ieee802.15.4 standard unit min. typ. max. internal voltage ? 1.45 ? ? v rf input frequency 2405 ? 2480 min. 2405/ max. 2480 mhz receiver sensitivity per = 1% psdu length = 20 octets interframe spacing 12 symbols (ieee802.15.4 minimum spacing) ? ?95 ?85 ?85 or less dbm maximum input level per = 1% 0 ? ? ?20 or more dbm adjacent channel rejection +5 mhz per = 1% prf = ?82 dbm 0 ? ? 0 or more db ?5 mhz 0 ? ? alternate channel rejection +10 mhz per = 1% prf= ?82 dbm 30 ? ? 30 or more db ?10 mhz 30 ? ? rejection > +15 mhz per = 1% prf= ?82 dbm 30 ? ? ? db < ?15 mhz 30 ? ? spurious emission 30 ? 1000 mhz renesas evaluation board ? ? ?57 etsi en300/328 dbm 1 ? 12.75 ghz ? ? ?47 symbol error tolerance ?80 ? 80 80 or less ppm rssi range prf (min) = ?75 dbm 40 75 ? 40 or more db rssi accuracy prf = ?75 to ?35 dbm ?6 ? 6 within 6db
r8c/3mq group package dimensions r01ds0044ej0100 rev.1.00 page 47 of 47 aug 11, 2011 package dimensions diagrams showing the latest package dimensions and moun ting information are available in the ?p ackages? section of the renesas electronics website.
c - 1 r8c/3mq group datasheet rev. date description page summary 0.10 nov 19, 2010 ? first edition issued 1.00 aug 11, 2011 all pages ?preliminary?, ?under development? deleted 4 table 1.2 revised, note 1 added 5 table 1.3 ?(d): under development?, (p): under planning? deleted 6 figure 1.2 revised 7 figure 1.3 revised 9, 10 table 1.5, table 1.6 revised 12 2.4 revised 14 3.1 revised 16, 17 table 4.2, table 4.3 revised 19 table 4.5 note 2 added 20 table 4.6 revised 24, 25 table 4.10, table 4.11 revised 32 table 5.6 revised 39 table 5.13 revised 46 table 5.22, table 5.23 revised, table 5.22 note 1 added all trademarks and registered trademarks are the property of their respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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